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Technical DFT Manager/Staff engineer with skills: -Chip level DFT plan and architecture definition, DFT specification creation and review with customer/design team co-work -Implement block/chip level DC/AC SCAN, MBIST/repair, BSD and IP macro test -Do all verifications on DFT structures, DFT patent generations & verifications, and deliver quality production ATE patterns -Deliver quality DFT timing constraints and support FE/BE team timing closure for tapeout -Support ATE bring-up, and debug the ATE patterns for production flow -Support logic scan/MBIST etc. DFT diagnosis for yield improvement Candidate requirements: -BSEE/ME/CE, MSEE/ME/CE is preferred (電子工程／微電子／通訊工程） -Hand-on experience in Synopsys (DFT Compiler/TetraMax/VCS) and Mentor Tessent MBIST and Chip DFT implementations are preferred -User of Perl or TCL is preferred -English communication skill -DFT experience > =5 years